As is well known in the art, wafer yield is a key factor in fabrication costs associated with the production of memory chips. The wafer yield is defined as the ratio of non-defective chips to total chips fabricate on a given wafer. Generally, as the integration density of a memory chip increases, the possibility of defects occurring in one or more memory cells of the memory chip also increases. Thus, the higher the integration density of a plurality of memory chips fabricated on a given wafer, the lower the wafer yield. The most effective approach for removing defects and thus improving the wafer yield, is to provide a redundancy circuit. A redundancy circuit provides memory cells of one or more redundant rows and/or columns, respectively, for replacing rows and/or columns of defective memory cells in a wafer level (or during a test mode). One example of the redundancy circuit is disclosed in U.S. Pat. No. 5,768,197, entitled "REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE", herein incorporated by reference ('197 patent).
As disclosed in the '197 patent, the replacement of a row of memory cells arranged along a word line comprising a defective cell is performed by programming an address of defective row or column in a decoder used to select a redundant word line or a redundant bit line. A well-known method for selecting the redundant word or bit line is by blowing a fuse using a laser or overcurrent. These methods, however, slow down the redundancy operation negatively affecting the fabrication cycle time. Accordingly, a need remains for a new redundancy scheme for replacing a column(s) of defective cell(s).